Complex application-specific integrated circuit (ASIC) and/or a system on a chip (SoC) designs use large numbers of hard macro cells, such as memory cells and/or mixed-signal devices. The macros are generally placed in clusters due to timing and/or physical constraints. The clustering of hard macro cells can be so large that signal delay on wire connections to, from and/or through the macro cell clusters becomes of concern for ASIC/SoC performance. Gaps between pairs of macro cells may be defined as channels when the gaps are smaller than certain threshold values. Buffering in the channels is an efficient way to speed up signals on wire connections. To enable buffering, the power grid integrity in the channels should be guaranteed. The power grid integrity in a channel may mean that there should be at least two power supply lines with opposite polarities (one power line and one ground line) existing in that channel. Typically, the size of the channels (width for vertical channels or height for horizontal channels) between the macro cells is not large enough to satisfy the power grid integrity requirement.
One conventional solution is to allocate larger channels to allow at least two power lines with opposite polarities to be present in the channels. However, this may lower the macro device placement density and therefore increase the size of the die chip, which increases the cost of the final products. Another conventional solution is to manually patch individual channels that are intended to be used. However, manual patching is a time-consuming, tedious and error-prone process, and the results may not be consistently repeatable.